MRF49XA
REGISTER 2-1:
STSREG: STATUS READ REGISTER (POR: 0x0000) (1) (CONTINUED)
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3-0
Note 1:
2:
3:
4:
5:
Note:
LBTD: Low Battery Threshold Detect bit
Indicates whether the battery or supply voltage is below the preprogrammed threshold limit.
1 = Supply voltage is below threshold
0 = Normal supply voltage feed
FIFOEM: FIFO Empty bit
Indicates whether the receive FIFO is empty or filled.
1 = FIFO is empty
0 = FIFO is filled
ATRSSI: Antenna Tuning and Received Signal Strength Indicator bit
Transmit mode:
The bit indicates that the antenna tuning circuit has detected a strong RF signal.
1 = Strong RF signal present
0 = Weak or absence of RF signal
Receive mode:
The bit indicates that the incoming RF signal is above the preprogrammed digital RSSI limit.
1 = RF signal is above the threshold value set
0 = RF signal is less than the threshold value set
DQDO: Data Quality Detect/Indicate Output bit
Indicates good data quality output.
1 = Quality data is detected
0 = Quality data is unavailable
CLKRL: Clock Recovery Lock bit
Indicates clock recovery is locked.
1 = Clock recovery locked
0 = Clock recovery unlocked
AFCCT: Automatic Frequency Control Cycle Toggle bit
For each AFC cycle run, this bit toggles between logic ‘ 1 ’ and logic ‘ 0 ’.
1 = AFC cycle has occurred
0 = No AFC in this cycle
OFFSV: Offset Sign Value bit
Indicates the measured difference or frequency offset of any AFC cycle (sign of the offset value).
1 = Higher than the chip frequency
0 = Lower than the chip frequency
OFFSB<3:0>: Offset bits
The offset value to be added to the frequency control parameter (internal PLL) (4) .
1 = Result is negative
0 = Result is positive
All register commands begin with logic ‘ 1 ’ and only the STATUS register read command begins with logic ‘ 0 ’.
This bit is multiplexed for Transmit or Receive mode.
See the FFBC bits (FIFORSTREG<3:0>) in Register 2-10 .
To get accurate values, the AFC should be disabled during the read by clearing the FOFEN bit
(AFCCREG<0>). The AFC offset value (OFFSB bits in the status word) is represented as a two’s
complement number. The actual frequency offset can be calculated as the AFC offset value multiplied by
the current PLL frequency step from CFSREG (FREQB<11:0>).
This bit is cleared after STSREG is read.
See Appendix A: “Read Sequence and Packet Structures” for the STSREG read sequence.
DS70590C-page 20
Preliminary
? 2009-2011 Microchip Technology Inc.
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